\section{Experiment Analysis and Case Studies}\label{sec:analysis}
\begin{table*}[tbh]
\caption{Physical planning results of 3D architecture}
\label{tab:tab2}\vspace{-5pt} %\scriptsize
\begin{center}
%\setlength{\tabcolsep}{0.2mm}
\begin{tabular}{c|c|c|c|c|c||c|c|c|c|c} \hline \hline
{\bf {Circuit}} & \multicolumn{5}{|c||} {\bf{Planning-after-Synthesis}} & \multicolumn{5}{|c} {\bf{Synthesis-during-Planning}} \\ \cline{2-11}
&\multicolumn{1}{|c|} {wire} & {area} & {peakT}
& {timing} & {run}
&\multicolumn{1}{|c|} {wire} & {area} & {peakT}
& {timing} & {run}\\

&\multicolumn{1}{|c|} {($um$)} & {($mm^2$)} & {} & {yield} & {time(s)}
&\multicolumn{1}{|c|} {($um$)} & {($mm^2$)} & {} & {yield} & {time(s)}\\\hline

$Alpha$  &210749 &15.49  &126.01 &85.2\% &363
         &210833 &15.44  &117.48 &94.3\% &2718\\\hline

$ami33$  &27911  &0.613  &164.60 &92.7\% &113
         &27435  &0.625  &154.65 &98.8\% &1165\\ \hline

$ami49$  &547491 &18.55  &130.22 &90.1\% &386
         &52090  &18.72  &124.19 &95.7\% &4590\\ \hline

$hp$     &124819  &4.45  &125.67 &88.7\% &16
         &119863  &4.51  &120.39 &96.5\% &871\\ \hline

$xerox$  &297440  &9.76  &127.21 &91.3\% &17
         &295768  &9.60  &119.64 &97.2\% &1615\\ \hline\hline

$Average$&1 &1  &1 &1 &1
         &0.99 &1.00  &0.95 &1.08 &12.24\\ \hline\hline

\end{tabular}
\end{center}
\vspace{-0.5cm}
\end{table*}


\begin{figure}[tbp]
  % Requires \usepackage{graphicx}
  \centering
  \includegraphics[width=0.45\textwidth]{fig/charac.pdf}\\
  %\vspace{-5pt}
  \caption{Delay and leakage power characterization of function units with multi-$V_{th}/V_{dd}$ and variation awareness.}\label{fig:charact}
  %\vspace{-15pt}
\end{figure}



In this section, we first present the experiment results of the design space
exploration for delay/power/variability in high-level synthesis, and then
demonstrate the effectiveness of our proposed \emph{synthesis-during-planning}
approach on several benchmarks.

\subsection{Results for Design Space Exploration in High-Level Synthesis}

We first show the variation-aware delay and power characterization of function
units. The characterization is based on NCSU FreePDK 45nm technology
library~\cite{URL:freepdk}. Variations on two device parameters, \emph{channel
length} and \emph{oxide thickness}, are set with relative deviations
($\sigma$/$mu$) to be $5\%$, respectively. The voltage corners for the
characterization are set as: $V_{th}^L = 0.37V$, $V_{th}^H = 0.56V$, $V_{dd}^L
= 0.9V$, $V_{dd}^H = 1.1V$. The characterization results for five function
units, including two 16-bit adders \emph{bkung} and \emph{kogge}, two
8-bit$\times$8-bit multipliers \emph{pmult} and \emph{booth}, and one 16-bit
multiplexer \emph{mux21}, are depicted in Fig.~\ref{fig:charact}. In the
figures, the color bars show the nominal case values while the error-bars show
the deviations. It is clearly shown that with lower $V_{dd}$ and/or higher
$V_{th}$, power consumptions are reduced at the cost of delay penalty.
 %Moreover, for the delay distributions in Fig.~\ref{fig:charactdelay}, the average $\sigma/\mu$ ratio goes up from $0.047$ in the top-left, to $0.059$ in the bottom-right. We can explore this trend further in Fig.~\ref{fig:trend}, where the delay and power distributions of the function unit \emph{bkung} is sampled at a third $V_{th}$ of $0.45V$. The plotted curves show that the magnitude of delay variation increases for higher $V_{th}$ units, which means larger probabilities of timing violations if these high $V_{th}$ units are placed on near-critical paths. This again calls for the deployment of statistical analysis approaches.

%\begin{table}[tbp]
%\centering
%\scriptsize
%\caption{The profile of test benchmarks}\label{table:bench}
%%  \vspace{-3pt}
%\begin{tabular}{|c|c|c|c|c|}
%\hline
%Name & \# nodes & \# edges & \# add & \# mult \\ \hline\hline
%EWF & 34 & 49 & 20 & 12 \\ \hline
%%PR & 44 & 132 & 26 & 16 \\ \hline
%WANG & 52 & 132 & 26 & 24 \\ \hline
%MCM & 96 & 250 & 64 & 30 \\ \hline
%%HONDA & 99 & 212 & 45 & 52 \\ \hline
%DIR & 150 & 312 & 84 & 64 \\ \hline
%STEAM & 222 & 470 & 105 & 115 \\ \hline
%\end{tabular}
%\end{table}

With the variation-aware multi-$V_{th}/V_{dd}$ resource library characterized,
we performed design space exploration for power reduction on a set of
industrial high-level synthesis benchmarks. The dynamic power consumption of
function units is estimated by Synopsys \emph{Design Compiler} with
multi-$V_{th}/V_{dd}$ technology libraries generated by \emph{Liberty NCX}. In
this work with FreePDK 45nm technology, the dynamic power is about 2 times of
the mean leakage power.



\begin{figure}[!btp]
  % Requires \usepackage{graphicx}
  \centering
  \includegraphics[width=0.45\textwidth]{fig/result3.pdf}
    %\vspace{-10pt}
  \caption{Design space exploration on timing
and power yield of the synthesized design.}\label{fig:result3}
    %\vspace{-10pt}
\end{figure}

%Fig.~\ref{fig:result1} shows the results in terms of power yield improvement with multi-$V_{dd}$ technique only, which means only the resource units with nominal threshold voltage $V_{th}^L$ (but different $V_{th}$) can be selected during the resource binding process. The average power yield improvements under timing yield constraints 99\%, 95\% and 90\% are 9.4\%, 15.7\% and 19.5\%, respectively.
%
%Fig.~\ref{fig:result2} shows power yield improvement with multi-$V_{th}$
%technique only, which means only the resource units with nominal supply voltage
%$V_{dd}^H$ can be selected. In this case, no level conversion is needed so
%there is no overhead for level converters. The average power yield improvements
%against worst-case delay based approach, under timing yield constraints 99\%,
%95\% and 90\% are 6.6\%, 8.5\% and 11.0\%, respectively. At timing yield 95\%,
%the average power yield improvement (8.5\%) is smaller than the LC-Avoidance
%case (10.3\%) in Fig.~\ref{fig:result1}, which shows that using multi-$V_{dd}$
%resource units can further improve the power yield.

Fig.~\ref{fig:result3} shows the power reduction of the synthesized design
compared with conventional single-voltage design. The average power reductions
against conventional worst-case based design, under timing yield constraints
99\%, 95\% and 90\% are 11.7\%, 21.0\% and 27.2\%, respectively. It is clearly
shown that, the power reduction largely depends on how much timing yield loss
is affordable for the design. This testifies the necessity of design space
exploration for a well balanced timing yield and power trade-off.

\subsection{Results of the Incorporated 3D Physical Planning Flow}
For the experiments on 3D physical planning, we use an Alpha-like detailed
microprocessor with the IVM verilog model~\cite{URL:IVM}, as well as several
MCNC benchmarks. The processor model is synthesized with FreePDK 45nm
technology library. The power density of each module is set between $1-5
W/mm^2$. The designs are split into two layers of a 3D IC, and the delay and
area overhead on through-silicon-vias (TSVs) are not accounted for the sake of
brevity. The physical planning flow is implemented in C++ and experiments are
conducted on a Linux workstation with a 3.2GHz dual-core CPU.

We compare the results with the conventional \emph{planning-after-synthesis}
flow as shown in Table~\ref{tab:tab2}. The left half of the table displays the
total wirelength, the chip footprint, the peak temperature of the chip, and the
overall timing yield for the conventional approach, while the right half shows
the results for our proposed approach, respectively. The cost factors are set
in order that the total wirelength and the chip footprint are kept unchanged,
while the rest two factors are to be optimized. Results over the benchmarks
show that the proposed \emph{synthesis-during-planning} approach can reduce the
chip peak temperature by 6.6~$^{\tiny\textrm{o}}$C on average, and improve the
overall timing yield by 8\%, without causing overheads on wirelength or chip
area. The benefits come from the fact that low-power or low-variability
alternatives of modules which fit the needs best, are placed on the critical
spots, while the slightly expensive modules in terms of power or area, are
introduced at non-critical locations. This demonstrates the effectiveness and
necessity that extra high-level design space exploration is used during the
physical planning of 3D IC design. Due to the iterative optimization, the run
time of the proposed approach increases by about 10 times, but is still in an
acceptable range for a design flow starting from system-level specifications
and generating placed RTL netlists.

 \vspace{5pt}



\section{Conclusion}\label{sec:conclusion}
This paper proposes an incremental system-level synthesis framework that
tightly integrates behavioral synthesis of modules into the layer assignment
and floorplanning stage of 3D IC design. Behavioral synthesis is implemented as
a sub-routine to be called to adjust delay/power/variability/area of circuit
modules during the physical planning process. Experiment results show that the
proposed synthesis-during-planning approach outperforms the conventional
planning-after-synthesis approach in reducing the chip power consumption, chip
area and the impact of process variability.
